Realization of Video Object Plane Decoder on Mesh On-Chip Network Architecture

H.-N. Nguyen, V.-D. Ngo, and H.-W. Choi (Korea)


Systems on a Chip, Networks on Chips, Mesh architecture, Video Object Plane, Simulation


System-on-chip (SoC) designs provide integrated solutions to challenging design problems in the telecommunications, multimedia, and so on. Present and future SoC are designed using pre-existing components which we call cores. Communication between the cores will become a major bottleneck for system performance as standard hardwired buss-based communication architectures will be inefficient in terms of throughput, latency and power consumption. To solve this problem, a packet switched platform that considers the delay and reliability issues of wires so called Network-on-Chip (NoC) has been proposed. This paradigm promisingly addresses the non-scalable problem of IPs connection in SoC. In this paper, we present interconnected network topologies and analyze their performances for a particular application under bandwidth constrains. Then we compare the performances among different ways of mapping the cores onto a Mesh NoC architecture. The comparison between Mesh and Fat-Tree topology is also presented. These evaluations are done by utilizing NS-2, a tool that has been widely used in the computer network design.

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