Leakage Power Dissipation in UDSM Logic Gates

H. Al-Hertani, D. Al-Khalili, and C. Rozon (Canada)


Static power dissipation, subthreshold current, gate tunnel ing current, GIDL current, logic styles, static leakage cur rent.


In this paper, a detailed leakage current analysis is per formed on various logic gates implemented in three cir cuit styles: conventional CMOS (CCMOS), pass transis tor logic (PTL) and complementary pass logic (CPL). The logic gates included in the analysis are the 2-input NAND, NOR and XOR gates, as well as the 4-input NAND and NOR gates and the full adder. SPICE simulations based on BSIM4 models were performed for all combinations of gates and circuit styles using the 45nm and 65nm BPTM CMOS processes [1]. The overall leakage current for each logic gate is char acterized by the leakage exhibited from the gate’s supply and inputs. Comparative analyses are also presented at the; (i)gate level, (ii)circuit style level and the (iii)technology level. At the gate level, the 2-input NOR gate consumed the least leakage current. While at the circuit style level, CC MOS exhibited the least leakage current for the 2-input and 4-input NAND and NOR gates. On the other hand, the PTL circuit style exhibited the least leakage current for the 2 input XOR and full adder implementations. All gates in all circuit styles exhibited approximately a 4-fold increase in leakage current in the 45nm technology when compared with the same implementation in the 65nm technology.

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