Design Issues for Bus Switch Systems in Deep Sub-micro Metric CMOS Technologies

M. Olivieri, F. Pappalardo, and G. Visalli (Italy)


Bus transfer, Encoding, Power demand, Very-large-scale integration


The high data-rate communication channels represent one of the most power-aware design problem, trying to decrease energy consumption maintain acceptable some other performance constraints. In this context, the bus-switch mechanism represents a novel and efficient bus encoding approach for low-power data off-chip buses. It is based on tentatively encoding, clustering, reordering and encoding a wide data buses according to a reordering pattern and a fixed coding function. Unfortunately, the hardware complexity limits the field of application in high capacity off-chip buses, where dynamic energy saving dominates the encoding power consumption. The paper addressed the design issues for bus-switch systems, employing industrial MOSFET models up to 90nm. Additionally, we evaluated the basic hardware resources: area, latency and power dissipation. Results indicated how future CMOS technologies enhance the bus switch’s field of application.

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