Virtual Hardware Management for High Performance Signal Processing

S. Erdogan, M. Eads, and T. Shaneyfelt (USA)

Keywords

FPGA, Virtual Hardware, Operating System, HDL, fault tolerance.

Abstract

The framework described in this paper uses an array of FPGA devices to implement a virtual hardware system that can be compared to the running of software on a traditional processor. Virtual Hardware is achieved by using the Field Programmable Gate Array (FPGA) technologies with on the fly partial programmability feature. The similarity between page size selection in a virtual storage system and selection of optimal area size for FPGA reconfiguration are compared and contrasted. Communication issues between modules that are mapped onto various parts of the FPGA are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files and potential for fault tolerance is examined in comparison to traditional operating system design choices.

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