G. Chiorboli, S. Dondi, C. Morandi, and D. Vecchi (Italy)
Pipelined ADC, background calibration, FPGA.
The design flow of a pipelined ADC with DAC errors cor rection in the first stages requires tayloring the digital cor rection hardware to the process dependent uncertainties af fecting the weighting elements, which can be better ap preciated on first silicon. The described FPGA imple mentation of the correction hardware allows flexible and quick co-development of the analog and digital sections of the converter. A novel error correction scheme based on weighting capacitor rotation is applied.
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