H. Zhang and E.I. El-Masry (Canada)
Flip-flop, prescaler, power consumption.
This paper proposes a novel low power, glitch free and general purpose D flip-flop circuit. Some published flip flops are studied and a modification is carried out to reduce power consumption. The proposed flip-flop is characterized and compared with the published one for reliability and power consumption. A 128/129 dual-modulus prescaler based on the proposed flip-flop using the 0.18um CMOS technology is also presented. It includes a synchronous counter divide-by 4/5 and an asynchronous counter divide-by-32. Input and output buffers are also included in the circuit. The simulated operating frequency and the power consumption of the prescaler are 2.5GHz and 6.57mW, respectively by using a single 1.8V supply voltage.
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