The Algorithm of 16-Bit Scrambler in Parallel for PCI Express

W.-O. Kwon, K. Park, M.-J. Kim, and H.-J. Kwon (Korea)

Keywords

Scramble(r), De-scramble(r), PCI Express, Linear Feedback Shift Register (LFSR)

Abstract

This paper describes an implementation and analysis of scrambler/descrambler for Physical layer of PCI Express device. When a binary bit stream being a high frequency of bit transition, electromagnetic interference (EMI) may be generated. These EMI noise is significant to PCI Express transmission line having 2.5Gbps bit stream. By scrambling the transmitted data, repetitive patterns can be eliminated so EMI noise removed. PCI Express uses Linear Feedback Shift Registers (LFSR) to scramble the data. This paper proposes the 16-bit parallel scrambler algorithm. Parallel scrambler/descrambler have pre calculators that can get the value to be used as input value of LFSR in next state.

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