An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding

C.-M. Chen and C.-H. Chen (Taiwan)


Deblocking Filter, H.264/AVC, Memory Reference, Video Coding.


In this paper, we propose an efficient architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use eight forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two filter units to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called “Pipeline Buffer Shift Register (PBSR).” As a result, the performance of PBSR is 22.5% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced to 37% and 75% respectively compared to the basic and advanced architectures of the previous proposals.

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