Chin-Yung Chen, Jenn Tang, Dong-Liang Lee, and Jih-Fu Tu
Data prefetching register (DPB), data reuse register (DRR), prefetching miss, prefetching hit
The authors introduce a new data prefetching technology that includes two schemes: instruction recognizing (IRing) and the data- prefetch buffering (DPB). The IRing is achieved by the instruction register, comparer, and the previous table. The DPR is implemented to the data reuse register and the data prefetching register. The authors build this new data prefetcher for reducing the accessed latency time of needed data and for improving the processor performance. The evaluation results in terms of the throughput show that the proposed data prefetcher is on average more effective than the pipeline processor. For this proposed data-prefetching scheme, the throughput improvement is 1.32 times the pipeline processor one’s.
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