S.R. Parr, K. Koutsomyti, V.A. Chouliaras, and D.J. Mulvaney (UK)
Signal Processing, Coprocessor, Embedded systems,Speech coding.
This paper presents the results of an investigation in using configurable scalar and vector coprocessors to accelerate the G.723.1 and the G.729A speech standards. Architecture exploration via the implementation of custom scalar and vector instructions has resulted in a reduction by up to 70% of the total number of instructions executed. The proposed accelerators are designed to be attached to a configurable, embedded RISC CPU where they make use of the host register file and load/store infrastructure.
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