J. Pratt, M. Aydin, and T. Chen (USA)
Neural Networks, VLSI Chip Design, RC Extraction, OPC.
A fast, accurate, and inexpensive technique of resistance and capacitance (RC) extraction on the interconnect wires of an integrated circuit was developed. With this technique, a neural network, given the original drawn shapes of the interconnect wires from the design process, predicts the shapes of the interconnects in a layout after the manufactur ing process. These interconnect layouts are then analyzed by a MATLAB program to determine their corresponding RC values. The RC values for the drawn and actual printed layouts are compared, along with the RC values for layouts obtained from Calibre OPC tool. The resistance values ob tained from the neural network produced layouts are within 5% of their Calibre counterparts, and the capacitance val ues were within 1% of the capacitance values extracted from layouts obtained from Calibre OPC.
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