Z. Stamenković, G. Panić, U. Jagdhold, H. Frankenfeldt, K. Tittelbach-Helmrich, G. Schoof, and R. Kr
Processor library, ASIC module, synthesis, and layout
The paper presents a specific approach to SoC design, aimed to provide a library of ASIC modules reusable in standard digital design flow. It familiarises you with the concept of library and its hierarchy. Also it describes how to specify, synthesise, layout, verify, and reuse ASIC modules.
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