M.R. Salehnamadi (Iran)
Non-blocking, Test, Fault-tolerance, MIN
In this paper, CLOS interconnection network is implemented with some modifications in middle stage. With a little additional hardware, fault tolerance is added to non-blocking three stage CLOS MIN. Internal test is in BIST form and faulty pins of boxes are marked in a reference memory. Additional hardware is used to simplify routing algorithm and in fault occurrence it is used to cover the fault. Additional hardware is only 8% and routing speed is O(1).
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