Sub-70 ps Full Adder in 0.18 µm CMOS Current-Mode Logic

E.J. Brauer (USA) and Y. Leblebici (Switzerland)


: current-mode logic, CML, CMOS, fulladder


This paper presents a single-bit full adder in MOS Current-Mode Logic with fast delays and low power compared to configurations previously reported. Our low power full adder exhibits post-layout carry-in to carry-out delays of less than 70 ps and can be utilized as building blocks in very high performance datapaths. The circuits are designed and simulated in a 0.18 m CMOS process and VDD of 1.8 V.

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