Y. Yin, H. Klar, and P. Wennekers (Germany)
Analog circuits, integrated circuits, Analogto-digitalconversion, sigmadelta modulation, simulation
A novel noise-shaping 3-1 cascaded two-stage sigma delta analog-to-digital converters (ADCs) architecture for broadband communication applications has been developed at a low oversampling ratio (OSR) of 8. The first stage is realized by a low-harmonic distortion single feedback 3rd -order architecture employing a high-order modified FIR noise-transfer-function with a 4-bit quantizer. The second stage is realized by a first-order multi-bit architecture. In comparison with traditional cascaded and single-loop high-order sigma-delta ADC architectures, the simulation shows, that these arrangements can significantly suppress not only the high frequency in-band quantization noise, but also the quantization noise leakage caused by integrator gain mismatching, even suppress the non-idealities of circuits such as finite open-loop gain of opamps, as well as the nonlinear effects of the integrator caused by the nonlinearity of opamps. Therefore, the proposed architecture can effectively achieve high resolution at the low OSR of 8 for high-speed applications.
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