E.J. Brauer (USA) and Y. Leblebici (Switzerland)
: prefix adder, current-mode logic, CMOS,low noise, MCML
This paper presents 3 adders of 8, 16 and 32 bit operands using MOS Current-Mode Logic in a prefix adder architecture with minimum logic levels and fan-out of two. The 32-bit adder exhibits delays of less than 530 ps for nominal conditions with a power supply current spike of only 1.2% of the nominal current. The circuits are designed and simulated in a 0.18 m CMOS process and VDD of 1.8 V.
Important Links:
Go Back
