Open-Loop Current Sense Amplifier

A. Varde, S. Shah, and A. Núñez (USA)


Digital Circuits and Systems, Sense Amplifier, Memory,VLSI


This paper presents a generic circuit topology for high per formance sense amplifiers. The proposed circuit topology provides high-quality data sensing for long column SRAM core arrays with very large bit-line capacitances. Fast re sponse times, reduced power consumption and low sensi tive to bit-line capacitance are the most predominant ad vantages of the proposed circuit topology.

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