O. Cadenas and G. Megson (UK)
Jayant Quantizer, adaptive quantization, FPGA, multiphase clocking, pipeline, DLLs.
A fully pipelined implementation in FPGA hardware of a backward adaptive scalar quantizer known as Jayant quan tizer is presented. The implementation combines a fast sys tolic formulation of a uniform scalar quantizer with a multi phase pipeline clocking mechanism based on embedded Delay-Locked Loops (DLLs) of modern FPGA devices. This combination shows that traditional fixed quantization based on look-up tables can be replaced by dynamic and adaptive quantizer circuits fast and small enough to be in tegrated into totally hardware solutions of standard lossy compression techniques.
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