2 Gb/s Decision Feedback Equalizer in 3.3 V 0.35 µm CMOS

H. Bengtson and C. Svensson (Sweden)


comparator, current summation, decision feedback equalizer, feedback filter, parallelism, intersymbol interference, Schmitt trigger


A 2 Gb/s decision feedback equalizer is implemented in a 0.35 m CMOS process and experimentally demonstrated. Speed is enhanced through optimization of the unavoidable loop in a decision feedback equalizer, parallelism, differential current mode frontend, fast sense amplifier style comparators and single-phase flip-flops.

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