Low Power Motion Estimator Architecture with Leakage Power Reduction in Deep Sub-Micron SoC

G.S. Yeon, C.H. Jun, T.J. Hwang, S. Lee, and J.-K. Wee (Korea)


-- deep sub-micron, leakage current, multimedia SoC, motion estimation, mega-block shutdown, early break-off


--This paper proposes a motion estimator architecture to reduce the power consumption of the most power-consuming motion estimation method when designing multimedia SoC with deep sub-micron technologies below 0.13m having large leakages. The proposed architecture considers both dynamic and static power consumption, while conventional architectures consider only dynamic power consumption. In the proposed scheme, it exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, mega block shutdown method considering power line noise is also employed. From the simulation results, power consumption of the proposed architecture was reduced to about 60%. If considering the increases of subthreshold leakage current and leakage current by heat dissipation from chip's operation, the proposed architecture can become one of efficient methods of static power reduction during active operation while it goes worse in conventional architectures.

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