Multiple Carry Asynchronous Estimated Adder

E.M. Ashmila, S.S. Dlay, and O.R. Hinton (UK)


- Arithmetic Circuit, High Performance Adder, Fast Adders, Estimated Carry, Multiple Carry Prediction.


Addition is one of the most important operations in any digital systems or processors because the performance of processors is significantly influenced by the speed of their adders. In this paper a novel high performance adder based on the statistical approach with multiple carries for prediction is presented. A simulation for this 32-bit adder design has been performed using a 0.125 m CMOS technology, and the simulation results shows that this new adder design can achieve dramatic speed advantages over other adders. The delay-area product comparison shows a saving of 44.2% over a ripple adder, 41% over carry select adder; with ripple adder elements, and over 26% on carry select look-ahead adders.

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