V.A. Chouliaras, J.L. Nunez-Yanez, and S. Agha (UK)
Video coding, multimedia processing, coprocessors,computer architecture
We discuss the architecture specification, RTL development and ongoing physical implementation of a parametric vector/SIMD accelerator for real-time MPEG2 encoding. The MPEG2 TM5 reference code was systematically optimized through tapping the Data-Level Parallelism (DLP) of the inner loop of Motion Estimation (ME) via custom vector extension instructions. We show that these instructions reduce the computational complexity of the encoding process by up to 60% for full search motion estimation. The combined RISC CPU/Vector accelerator is being implemented as a hard macro. This work focuses on the flow from algorithmic C to a placed and routed database for the datapath of the vector accelerator in a high-performance 0.13 m, 8-layer copper silicon process, for a number of register file configurations.
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