Wormhole Routers for Network-on-Chip

J. Ge (USA)

Keywords

systemonchip, torus network, deadlockfree routing,hardwired dateline, escape channel, costeffectiveness

Abstract

The cost-effectiveness of routers is critical in integrating an interconnection multicomputer network on a single chip. The intent of this paper is to find a cost-effective wormhole router that is suitable for a system-on-chip implementation of a torus network. A newly developed scheme is used to enhance the performance of previous routing algorithms by introducing a hardwired dateline and by managing buffers of various virtual channels differently. Two algorithms derived from this scheme are compared with previous algorithms by not only performance in terms of throughput and latency but also implementation cost in terms of chip area and operating frequency. The paper also proposed a promising single chip multicomputer based on the cost-effective router and off-the-shelf processing elements.

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