Distributed Variable-length Packet Scheduling in a PPS Switch

X. Liu, J. Wu, Y. Guo, and J. Lan (PRC)

Keywords

high performance router, packet scheduling, cell scheduling, QOS, multistage buffering

Abstract

The Internet is facing two main problems simultaneously: faster switching/routing infrastructure and Qualities of Service (QOS) guarantee. Using conventional lower speed devices, it is theoretically possible for a Parallel Packet Switch (PPS) to emulate a first-come first-served (FCFS) output-queued (OQ) packet switch. But, PPS solutions are impractical because of high communication complexity. In this paper, a novel architecture of a PPS switch, which emulates Push-in-Arbitrary-out (PIAO) OQ high-speed switch, is present. And, a Distributed Variable-Length Packet Scheduling algorithm (DVLPS) providing QOS guarantee reducing the complexity is also present.

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