M. Li, X. Wu, X. Zhu, and H. Wang (PRC)
GA, System Level Synthesis, Multiprocessors, Low Power
Embedded systems are nowadays becoming more and more distributed and intensively coupled with the environment. For I/O intensive distributed embedded systems, the power consumption on I/O devices is as important as that on PEs (Processing Elements). Most work on power aware I/O scheduling considers only independent coarse grain tasks on uni-processor. More over, energy and time penalty is seldom taken into account. The existing models are too inaccurate to deliver the great potential of low power system level synthesis. In this paper, a flexible model, which is based on TG (Task Graph), is presented for I/O intensive distributed embedded system in fine grain manner. More importantly, we present a novel I/O aware system level synthesis algorithm that is based on Hierarchical GA (Generic Algorithm). In the proposed algorithm, outer loop deals with task assignment, while inner loop deals with scheduling on both I/O devices and PEs.
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