Compile-time Simulation for Low-Power Optimization using SystemC

A. Jones, X. Tang, and P. Banerjee (USA)


Hardware synthesis, SystemC, low-power, optimization


Power modeling and estimation in state of the art electronic design automation (EDA) tools is still in its infancy. Current automated hardware design methodologies continue to focus on area and performance as metrics for success for their generated implementations while leaving power consumption as an after thought. Many EDA tools do not consider power as an optimization metric at all and those that do often utilize static power estimation that can be wildly inaccurate. This paper describes a completely automated compile-time simulation strategy specifically for power characterization within a high-level synthesis flow. The synthesis tool can read an algorithmic description in C and automatically generate a simulator for the algorithm built with the SystemC language for system level simulation. It also automatically generates an associated probabilistic input dataset for use in simulation. The simulation is executed as part of the compilation flow to generate characterizations for the various functional units generated through synthesis or contained in an intellectual property (IP) library. These functional units are pre-characterized with power consumption information based on several input parameters including input signal probability, average transition density, and input spatial correlation. The resulting simulation data is combined with the characterization data in the compiler which allows the creation of a switching and power table that corresponds to the activity of the algorithm in hardware. These tables can then be used to support a variety of power optimization strategies which may now leverage actual program execution statistics rather than less accurate static power estimation methods. Experimental results on the described simulation methodology for a set of six benchmarks show speedups of about 10X in execution times compared to conventional approaches at the RTL level.

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