Modeling and Simulation of Fast Floating-Point Function Generation

P. O’Grady and M. Watson (USA)

Keywords

Abstract

A VHDL model that implements a hardware-oriented floating-point function generation algorithm is simulated and tested. The model implements the function generator as a six-stage pipeline. The pipelined implementation and results of sub-unit, unit, and system tests are presented

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• DOI:
• From Proceeding (415) Modelling, Simulation, and Optimization - 2003

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