Synchronous State Machine Design Methodologies with VHDL and Implementations using CAD Tools

R. Sandige, A. Liddicoat, and B. Mealy (USA)


Computer Aided Design, VHDL Design Methodologies, VHDL for Synthesis, Design Implementation in a CPLD


Several different methodologies can be used for designing Synchronous State Machines with VHDL [1], [2], [3], [4], [5], [6], and [7]. Three different design approaches are presented using state-of-the-art Xilinx ISE FoundationTM Series Software [8]. These design approaches include the StateCAD Method, Equation Method, and State_Type Method. After obtaining the VHDL code for the three design methods, each design is compiled or synthesized to verify the VHDL code is syntactically correct. VHDL test-bench code is created using a test-bench waveform generator. The ModelSim simulator is used to check the functionality of each design by running the VHDL test-bench code with the state machine design source code. After the designs are shown to simulate correctly, jedec files are generated for a CPLD. A DigilabTM XCR Plus board containing a CoolRunner CPLD with 64-macrocells is used to implement the designs in hardware. The designs are downloaded into the CPLD in order to demonstrate proper operation. The clock speed is set such that correct circuit operation can be verified via switch inputs and LED outputs.

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