Modeling, Simulating, and Implementing Clockless Finite State Machines

R. Sandige, A. Liddicoat, and B. Mealy (USA)


Computer Aided Design, Modeling, Clockless Finite StateMachine Design, Programming CPLDs.


This paper discusses the development of several digital Pulse Mode (Clockless) Finite State Machines [1], [2], [3], [4], [5], and [6] using a CPLD (Complex Programmable Logic Device [1]). Xilinx ISE FoundationTM Series Software [7] CAD (Computer Aided Design) tool comprises our development environment. The hardware platform is a COTS (commodity-off-the shelf) board containing a CPLD and devices such as push button switches, slide switches, and LEDs (Light Emitting Diodes) to directly interface with the CPLD. The CPLD is reprogrammable which allows it to be used over and over again during design development and testing. A simple coin operated vending machine and a combination lock are presented as practical examples. In our approach, circuit designs are entered using schematic capture tools. The CAD software generates VHDL code [1], [8], [9], [10], and [11] from the schematic. Then the VHDL code is used to generate a jedec file that is downloaded into the CPLD. A test bench waveform generator creates VHDL test bench code, which is used by the simulator (ModelSim) to verify the functionality of each design. The designs are also tested using the switches and LEDs of the hardware platform. A constraint file is used to specify the dedicated CPLD pins for the input/output components, i.e., the switches and LEDs.

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