D. Q. Minh, L. Bengtsson, and P. Larsson-Edefors (Sweden)
: DSP architecture, power estimationsimulation.
High performance, low power and low cost will continue to be driving factors for digital signal processor (DSP) and embedded computer systems of the future. There are lots of research efforts dedicated for reducing both dynamic and static power consumptions in all design levels ranging from the circuit-level to the architecture level and the algorithm-level. In all these levels performance-power simulation/estimation tools play a very important, even decisive role. This paper describes the DSP-PP a simulation tool for estimating power dissipation and performance of parallel DSP architectures. The DSP-PP consists of a Cycle-level Performance Simulator capable of and extendable to simulate any parallel DSP architectures and generate accurate performance statistics, and a Power-Dissipation Estimator capable of estimating both static and dynamic power consumptions. DSP-PP uses a modified version of Wattch's power models to estimate the power dissipation of each DSP component as well as power consumption of the entire DSP parallel architecture. The Billions of Operations Per Second Inc. (BOPS) ManArray is a family of parallel DSP architectures whose implementations can be found in many commercial digital signal processing, video/ image processing, and communication applications. Therefore, in the first step, in order to evaluate and present its own simulating capabilities the DSP-PP uses the ManArray architecture as a core DSP architecture to perform power and performance estimations for several DSP parallel architecture configurations.
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