L. Villa, O. Camacho, A. Villar, C. Osuna, G. Santana, and M. Romero (Mexico)
Memory, Cache, Speculative, Prediction
Serialized cache access has been a strategy proposed in others' works to reduce the latency penalty introduced in a two-way set-associative cache. In this paper we present a novel mechanism, which provides a better or the same miss rate as a two-way set-associative cache, and with similar access time as a direct mapped cache. We use an address prediction strategy to select the correct cache set entry in a virtually partitioned direct mapped cache.
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