Design Planning in Hardware Compilers

S.O. Memik (USA)

Keywords

Reconfigurable Systems, Hardware Compiler, HighlevelSynthesis

Abstract

Along with the fast evolution of programmable and recon figurable systems, hardware compilers also advanced to wards enhanced capabilities and optimization power. The responsibility of early hardware compilers was to map a subset of procedures or time critical computations onto hardware, where reconfigurable hardware was mostly uti lized as a co-processing unit. A new generation of hardware compilers are needed to create frameworks for mapping significantly complex applications onto programmable de vices. This can be achieved by empowering hardware com pilers with new methodologies to increase their efficiency. Design Planning is one such concept. In this paper, we in troduce techniques to enable a smooth, non-restrictive in teraction between different compilation stages. These tech niques are collectively referred to as Design Planning.

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