Scalable Pipeline Insertion in Floating-point Units for FPGA Synthesis

I. Ortiz and M.A. Jimenez (Puerto Rico)


FPGA, floating-point arithmetic, variable pipeline, scalable hardware


Most modern arithmetic processors rely on pipeline tech niques to obtain high throughput. This work reports the development of scalable, floating-point (FP) arithmetic op erators with a variable number of pipeline stages. An al gorithm for pipeline insertion was developed and used for FP Multiplication and FP Addition. The use of this algo rithm enables operating frequencies up to 175MHz when implemented on a Xilinx Virtex II FPGA. The developed units offer scalability in terms of precision and range. Fu ture work includes the automation of the process and the inclusion of the algorithm into FP square root and division units.

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