C. Sánchez-López, E. Tlelo-Cuautle, F. Sandoval-Ibarra, and A. Díaz-Méndez (Mexico)
Noise Figure, Symbolic Analysis, Analog Modeling, CMOS Circuits
A novel symbolic-analysis technique oriented to compute Noise Figure (NF) in CMOS circuits, is presented. To com pute NF in a CMOS circuit, a nullor-based model for the three and four terminals MOSFET, is proposed. To demon strate the suitability of the proposed technique, an illus trative example where the NF is computed using the pro posed method and compared with HSPICE simulations, is given. Finally, NF in a CMOS-circuit generating gaussian functions, biased in weak inversion and working in current mode is computed.
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