Z. Guo and P. Nilsso (Sweden)
VLSI, MIMO, V-BLAST, Square Root Algorithm, FiniteWord Length Analysis
A low complexity VLSI architecture of the square root al gorithm is proposed for MIMO detection. As a modifi cation to the traditional QR triangular array based archi tecture, the proposed architecture significantly reduces the area and power consumption with virtually no performance or throughput degradation. The finite word length effects specific to the architecture are analyzed considering trade offs between the performance and the hardware cost. The proposed VLSI architecture is implemented on a VirtexE series Xilinx FPGA. For a 4-transmit and 4-receive anten nas MIMO system using QPSK modulation scheme, a de tecting throughput of 80 Mb/s can be achieved.
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