C. Rajagopal and A. Núñez-Aldana (USA)
Analog, Synthesis, Performance Estimation
In this paper, the authors present a methodology to synthesize CMOS analog circuits from high-level cir cuit specifications into transistor net-lists. A two-step approach is used to speed up the design process and achieve high quality designs. It the first step, a fast analog performance estimator is used to perform a global circuit sizing, where a large design exploration space is encountered. In the second step, SPICE cir cuit simulations are used during a detail circuit siz ing achieving high accuracy results. The synthesis en vironment considers several performance parameters into account, and it relies on a genetic algorithm based heuristic method to search for a solution in a large design-space.
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