Align Unit for a Configurable DSP Core

C. Panis, R. Leitner, H. Gruenbacher (Austria), and J. Nurmi (Finland)


VLIW, unaligned program memory, configurable DSP, align unit


Increasing system complexity of SOC applications leads to an increasing requirement of powerful embedded DSP processors. To increase the performance of DSP processors the number of parallel executed instructions has been increased. To program the parallel units VLIW (Very Long Instruction Word) has been introduced. Programming the parallel units at the same time leads to an expanded program memory port or to the limitation that only a few units can be used in parallel. Traditional VLIW architectures feature poor code density and therefore high area consumption of the program memory. To overcome this limitation the paper describes the align unit, which allows using unaligned program memory without any limitations on the core performance. The architecture, some implementation details and the influence on area consumption and power dissipation of the align unit are discussed in this paper. The align unit is part of a development project for a configurable DSP.

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