A Medium-grain Reconfigurable Cell Array for DSP

J.G. Delgado-Frias, M.J. Myjak, F.L. Anderson, and D.R. Blum (USA)

Keywords

Reconfigurable Cell Array, MediumGrain, VLSI Circuits and Systems, Digital Signal Processing.

Abstract

Digital signal processing (DSP) is an essential component of many applications, including multimedia and communications systems. The recent surge in wireless and mobile computing underscores the need for high-performance low power DSP hardware. Reconfigurable hardware balances these requirements with development costs by providing system designers a viable alternative to custom integrated circuits. This paper describes a novel reconfigurable architecture for DSP applications. The device contains an array of medium-grain cells that can perform arithmetic, memory, and control operations. The main features of the architecture are as follows: flexible structures, variable word length, pipeline latches, and error correction. A prototype of the cell is being fabricated in 0.5-m technology. Circuit simulations indicate that the array achieves a clock frequency of 100 MHz even with this modest technology and a performance comparable to the highest-performance DSP processors today.

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