An Optimal Piece-wise Linear Strategy For Reference Voltage Variation in Time-based CMOS Imagers

X. Qi and J.G. Harris (USA)


Well Capacity, CMOS image sensor, Signal-to-Noise Ratio (SNR), Comparator delay, Dynamic Range (DR)


Time-based CMOS imagers are promising due to their high dynamic range and improved Signal-to-Noise Ratio (SNR) compared to conventional CMOS imagers. The illuminance on a pixel is encoded with the time that the pixel voltage drops below a global reference voltage. In order to guarantee that all pixels reach the reference voltage within one frame period, the reference voltage must be slowly varied. Thus far, there have been no systematic studies of the best reference voltage variation procedure for the continuous case. We formulate this optimization problem by considering the averaged SNR as the objective function and the required minimum time interval as the constraint. This formulation leads to a reasonable piece wise linear variation strategy. Finally, we also consider the effect of the non-zero comparator delay on this solution.

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