E.M. Ashmila, S.S. Dlay, and O.R. Hinton (UK)
Asynchronous Adder, Statistical Probability,Estimated Carry, Multiple Carry Prediction.
Recently a 32-bit asynchronous adder using a single probabilistic carry prediction attracted significant research interest worldwide. This paper demonstrates that the theory can be extended and theoretically, the adder can operate at the speed of a 16-bit addition for all inputs. Furthermore, this paper presents two carry control circuits for the 32-bit adder, to show that the performance enhancements for the proposed 32-bit adder. These are circuits are suitable for implementation in VLSI technology. The circuit has been simulated using HDL and the results are in line with the theory.
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