A Methodology to Reduce Computational Complexity in Analog Synthesis

A. Varde, S. Saldanha, and A. Nunez-Aldana (USA)


High level Analog synthesis, Computational Intelligence,Analog Circuit optimization.


This paper presents a novel methodology to synthesize and optimize analog circuits. Sharing techniques are used to minimize area while meeting system constraints. The methodology selects components from a pre-defined library using an intelligent factor (iFactor). The selection and merging processes are guided by a simulation-based process. The iFactor significantly reduces the computation time required for synthesizing and optimizing hierarchical representation of analog circuits. Experimental results show the effectiveness of the methodology in relatively short execution times.

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