Aspects About Some AES Candidate Algorithm Hardware Implementation

E. Mang, I. Mang, and C. Popescu (Romania)


Encryption, FPGA, Block cipher, VHDL, AES


: Devices such as Field Programmable Gate Arrays (FPGA) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementation of four of the Advanced Encryption Standard candidate algorithm finalists. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high throughput implementations, which are required to support security for current and future high bandwidth applications. The solutions will be compared in an effort to determine the most suitable candidate for hardware implementation within available FPGA.

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