Y. Linn (Canada)
QPSK, BPSK, lock, symbol, synchronization, SNR
This paper introduces a new lock detector for symbol tim ing recovery PLLs in QPSK receivers operating in AWGN channels. The detector necessitates only two samples per symbol, and these samples correspond to those required by the popular Gardner[1] timing error detector. The lock detector is characterized theoretically and through simula tions. It transpires that the lock detector is self normalizing, and that the channel ES/N0 ratio can be accu rately and easily estimated from the lock detector's value. A simple hardware structure is found for the lock metric computation process, which allows for its compact imple mentation in an FPGA or ASIC. The analysis is then briefly generalized to apply to BPSK.
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