M.R. Yuce and W. Liu (USA)
Subsampling, low-power receiver design, PSK
The subsampling process with a 1-bit A/D at the front-end of the receivers is a scheme that can reduce hardware complexity dramatically. It allows large power consuming circuits such as Automatic Gain Control (AGC), Phase Lock Loop (PLL) and mixers be eliminated or simply replaced with digital ones. In this paper we present extremely flexible and low power digital coherent PSK, differential PSK (DPSK) and double differential PSK (DDPSK) receivers using subsampling front-end via a 1 bit A/D. Analytical and simulation results of the error probabilty performance for the receivers are given. This low power implementation incurs a small, but acceptable degradation comparing to the conventional demodulators. Hardware realizations of each receiver model including some novel properties for low power application are also presented and compared to the conventional ones.
Important Links:
Go Back
