P. Guitton-Ouhamou, C. Belleudy, and M. Auguin (France)
low-power, consumption model, Digital Signal Processor.
The remarkable growth of personal computing devices, like portable desktops, require high speed processors with low power consumption. For example, integrate an increasing number of wireless telecommunication systems functionalisties requiring more and more efficient and powerful architectures. Architectures tend to include higher parallelism and deeper pipeline units. To counterbalance these architecture improvements, leading to energy consumption, low power techniques are implemented (as gated clock, techniques to prevent togglings, addresses optimized computation...). It is necessary to estimate the consumption of processors to reduce the dissipation of energy. In this paper, we propose some consumption models of two DSP processors. Comparison is done and differences are explained by data path. Because of the complexity of architecture, compilers ineffective, and models are at assembly level. We also propose to integrate these models in a performance estimator which allows programmers to work at C level. Indeed, telecommunication applications are written in C, it would be interesting to estimate the consumption at this level.
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