Deepa Sankar, S. Lakshmi, C.A. Babu, and K. Mathew
FPGA, FS-PDCC, model predictive control (MPC), HDL coder,ADC IP core
This paper discusses a simple and efficient rapid prototyping method for the field programmable gate array (FPGA) implementation of computationally intensive finite state-predictive direct current control (FS-PDCC). The MATLAB/Simulink hardware description language (HDL) coder generates optimised Verilog code from HDL- supported Simulink blocks to fit a low-cost target-Intel Altera MAX®10 FPGA. The proposed work exhibits an efficient resource utilisation of the FPGA with an excellent cost-performance trade- off. In addition, the implemented control algorithm shows superior output quality, validated in Simulink, and verified experimentally in a two-level three-phase voltage source inverter (VSI) prototype. This approach will assist the power electronic designers to implement complex control algorithms rapidly and efficiently without manual coding, reducing the design productivity gap.
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