A LOW-POWER WIRELESS DISTRIBUTED DYNAMIC NETWORK DESIGN CONCEPT: FFT PROCESSOR ARCHITECTURE

Vyasa Sai, Ajay Ogirala, and Marlin H. Mickle

Keywords

Radio frequency communication, low power design, distributed architecture, FFT, reconfigurable, programmable, passive processor.

Abstract

Power consumption has become a significantly critical aspect in processor designs used in wireless embedded devices. This paper proposes a novel concept of wireless distributed architecture for low-power using the design of a single-chip processor applicable for Fast Fourier Transforms (FFTs). This dynamic communication architecture consists of active powered and passive powered cells, which communicate with each other through RF signals. An active cell acts as a central controller for multiple power-constrained passive cells forming a star topology. The low-power design philosophies required for the segregation of the components of a single-chip processor into active and passive cells as well as for the passive cell processor implementation in such a distributed network are introduced in this paper. The major advantages of such design methodologies are not only low-power consumption but also reconfigurable integration of passive cells to the network, programmable passive cells, etc. The potential of the low-power distributed concept is established with reference to “Pulse oximeter – the instrument used to monitor blood oxygen levels.

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