R.K. Jena and G.K. Sharma
Multi-objective optimization, Network on Chip synthesis, energy model
Network on Chip (NoC) is a new paradigm for design core based System on Chip (SoC) which supports high degree of reusability and provides increase computation power. This paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh-based NoC in two systematic steps using multi- objective evolutionary algorithm. The main objective is to obtain the pareto mappings that minimized the energy consumption (com- putational and communicational) and link bandwidth requirement under performance constraints. The evaluation performed on three randomly generated benchmarks and a real application (M-JPEG encoder) to conform the efficiency, accuracy and scalability of the proposed approach. Our proposed approach saves up to 15–20% of energy and bandwidth requirements compared with the existing approaches.
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