|
531-019
|
A Novel Image Compression Algorithm for Hardware Implementation
S. Chen, S. Yang, and Q. Wu (PRC)
|
Abstract
|
|
|
531-059
|
GPU-Driven Recombination and Transformation of YCoCg-R Video Samples
D. Van Rijsselbergen, W. De Neve, and R. Van de Walle (Belgium)
|
Abstract
|
|
|
531-104
|
A New Nonlinear Image Sequences Filtering
M. Saeidi (Iran)
|
Abstract
|
|
|
531-105
|
A New Fuzzy Algorithm in Image Sequences Filtering
M. Saeidi, B. Saeidi, Z. Saeidi, and K. Saeidi (Iran, USA)
|
Abstract
|
|
|
531-109
|
A Visual
Method to Guide for a Mobile Robot with a Camera
S. Lili and S. Uchikado (Japan)
|
Abstract
|
|
|
531-122
|
An Efficient Image Retrieval through DC Feature Extraction
Y.S. Irianto, J. Jiang, and S.S. Ipson (UK)
|
Abstract
|
|
|
531-046
|
Realization of the Third-Order High-Pass Transfer Function
N. Stojković, M. Franušić, and M. Dozet (Croatia)
|
Abstract
|
|
|
531-079
|
System Design for Integrated DVB-H DTV Tuner
J. Xiao, R. Kulkarni, Y. Moon, and J. Silva-Martinez (USA)
|
Abstract
|
|
|
531-081
|
Programmable CMOS Interface for Resistive Bridges
A.J. Lopez-Martin and A. Carlosena (Spain)
|
Abstract
|
|
|
531-082
|
Two Proposals for CMOS V-I Converters with Optimized Linearity
A.J. Lopez-Martin (Spain, USA), J. Ramirez-Angulo (USA), and R.G. Carvajal (USA, Spain)
|
Abstract
|
|
|
531-083
|
CMOS Optical Transimpedance Amplifier Design for PAM Application
V.K. Shenoy, H. Shanmugasundaram, S. Jung, J. Gao, and Y. Joo (USA)
|
Abstract
|
|
|
531-087
|
High-Level Simulation of Substrate Noise in Mixed-Signal Integrated Circuits
M.J. Shanthi Prasad, M.N. Shanmukha Swamy, K.S. Gurumurthy (India), and B. Kim (USA)
|
Abstract
|
|
|
531-101
|
Analysis of Compound Noise in Nanometer Scale Circuits: Capacitive Coupling and Leakage Noises
P. Khaled, C.M. Tan, and M.H. Chowdhury (USA)
|
Abstract
|
|
|
531-124
|
A Driving
Circuit for the Thin-Disc Piezoceramic-Metal Structure Ultrasonic Actuator
F. Wen, I. Hsu, S.-T. Twu, and J.-J. Shieh (Taiwan)
|
Abstract
|
|
|
531-138
|
0.35
µm CMOS Band-Pass Switched-Capacitor Filter with Improved Capacitance
Matching
C.F.T. Soares and A. Petraglia (Brazil)
|
Abstract
|
|
|
531-029
|
An Automatic Synthesis Methodology for Synthesis of CMOS Ring VCOs
L. Wang and A. Nunez (USA)
|
Abstract
|
|
|
531-049
|
Improvements of the GCLP Algorithm for HW/SW Partitioning of Task Graphs
B. Knerr, M. Holzer, and M. Rupp (Austria)
|
Abstract
|
|
|
531-086
|
An Algorithm for Power Grid Optimization based on Dynamic Current Consumption
H. Ishijima, K. Kusano, T. Harada, Y. Kawakami, and M. Fukui (Japan)
|
Abstract
|
|
|
531-096
|
3D FEM
Analysis of EM Force on End Winding Structure for Electrical Rotating
Machines
M.S. Manna, S. Marwaha, and A. Marwaha (India)
|
Abstract
|
|
|
531-107
|
Ant Colony based Optimization Approach for Synthesis of MVL Functions
M. Abd-El-Barr (Kuwait)
|
Abstract
|
|
|
531-140
|
Clock-Tree
Synthesis for EMC-Aware Design
D. Pandini and G.A. Repetto (Italy)
|
Abstract
|
|
|
531-801
|
Re-Synthesis Approach to Engineering Change Orders (ECOs)
A. Vaidyanathan, A. Varde, S. Iyengar, S. Settikeri, and S. Subramaniam (USA)
|
Abstract
|
|
|
531-014
|
Design Issues and Implementation Strategies for Building On-Chip Voltage Level-Shifting Circuits
P. Lakshmikanthan and A. Nuñez (USA)
|
Abstract
|
|
|
531-067
|
Swift Transition Weight Analysis for Asynchronous Finite State Machines
J.-L. Yang, C.-F. Tai, and S.-M. Lin (Taiwan)
|
Abstract
|
|
|
531-069
|
A Product Line Engineering Approach to Designing System-on-Chips (SoC)
S.H. Chang, D.W. Cheun, T.K. Yu, and S.D. Kim (Korea)
|
Abstract
|
|
|
531-092
|
A Power
Allocation and Control Algorithm for Digital Subscriber Lines
A. Rashdi and N.M. Sheikh (Pakistan)
|
Abstract
|
|
|
531-108
|
A Design Method of FIR Filter with Variable Stopbands
S. Takahashi, N. Aikawa, M. Nakatani, and Y. Wakasa (Japan)
|
Abstract
|
|
|
531-112
|
Effects of Input Variations in Interconnection Trees
R. Sharma (India)
|
Abstract
|
|
|
531-137
|
Efficient Structure for Auralization using a Wavelet-based HRTF Model
J.C.B. Torres, M.R. Petraglia, and A. Petraglia (Brazil)
|
Abstract
|
|
|
531-142
|
A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip
N. Tabrizi and N. Bagherzadeh (USA)
|
Abstract
|
|
|
531-085
|
An Improved Hybrid Analog-to-Digital Converter Architecture using RSD-Cyclic and Sigma-Delta Architectures
Y.H. Atris and L.D. Paarmann (USA)
|
Abstract
|
|
|
531-094
|
Resettable Higher Order Delta-Sigma Converters for Imaging Applications
H. Durmus, A. Joshi, and J. Choma, Jr. (USA)
|
Abstract
|
|
|
531-129
|
Design
of a 3 GHz 6th Order Delta-Sigma Modulator in a 0.2 µm
GaAs Technology
E. Avignon, S. Guessab, R. Kielbasa, J.-M. Guebhard,
N. Fel, and J. Russat (France)
|
Abstract
|
|
|
531-132
|
A 91dB SOP-based Low-Voltage Low-Distortion Fourth-Order 2-2 Cascaded Delta-Sigma Modulator
C.-H. Kuo, S.-C. Chen, and K.-S. Chang (Taiwan)
|
Abstract
|
|
What are Digital Object Identifers?
The relevant topics for this conference include, but are not limited to:
Analog Circuits;
Digital Circuits and Systems;
Integrated Circuits;
RF and High-Frequency Circuits;
VLSI Circuits and Systems;
Systems on a Chip;
Nonlinear Circuits and Systems
Optoelectronic Circuits;
Power Electronics;
Neural Systems;
Cellular Neural Networks;
MEMS and Sensors;
Nanotechnology;
Computer-aided Design;
Biologically Inspired Circuits and Systems;
Communication Circuits and Systems;
Robotics;
Digital Signal Processing
Image Processing;
Pattern Recognition;
Visualization;
Speech Processing;
Communication Systems;
Wireless Communication
Multimedia;
Control Theory
Control Systems;
Fuzzy Logic;
Neural Networks;
Computational Intelligence;
Optimization;
Nonlinear Systems;
Fractals and Chaos;
Modelling;
Simulation;
Identification;
Artificial Intelligence;
Education; and
Applications.
