REDUCED SWITCHING ANALYSIS-BASED SPACE VECTOR MODULATION ALGORITHM FOR MULTILEVEL INVERTERS

Poonam Jayal and Gurumoorthy Bhuvaneswari

Keywords

Cascaded H bridge inverter, multilevel inverter, neutral pointclamped inverter, space vector pulse-width modulation, digital signalprocessor, Embedded Coder

Abstract

This paper proposes a generalized and mathematically less intensive algorithm for implementing space vector pulse-width modulation in multilevel inverters. It simplifies the space vector diagram (SVD) of a (2^n + 1)-level inverter, stepwise, into a basic two-level case using ā€œnā€ pivot vectors and proposes a considerable reduction in the switching analysis based on a noteworthy relationship elucidated and established between the switching sequences of the various two-level hexagons of the multilevel SVD. It is proposed that the switching sequences of a (2^n + 1)-level inverter with 6^n two-level hexagons in its SVD can be derived by investigating the switching combinations of merely 2^n two-level hexagons, irrespective of the voltage source inverter topology, thereby reducing the memory requirements for lookup tables and the computation time of the processor considerably. The algorithm has been successfully simulated in the MATLAB/Simulink environment and experimentally verified on the laboratory prototypes of multiple multilevel topologies. Experimental implementation using a digital signal processor (DSP) with the Embedded Coder tool from Simulink toolbox obviates the need for conventional DSP programming, adding to the simplicity of the proposed algorithm.

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